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Espressif Systems /ESP32-P4 /CACHE /L1_BYPASS_CACHE_CONF

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Interpret as L1_BYPASS_CACHE_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BYPASS_L1_ICACHE0_EN)BYPASS_L1_ICACHE0_EN 0 (BYPASS_L1_ICACHE1_EN)BYPASS_L1_ICACHE1_EN 0 (BYPASS_L1_ICACHE2_EN)BYPASS_L1_ICACHE2_EN 0 (BYPASS_L1_ICACHE3_EN)BYPASS_L1_ICACHE3_EN 0 (BYPASS_L1_DCACHE_EN)BYPASS_L1_DCACHE_EN

Description

Bypass Cache configure register

Fields

BYPASS_L1_ICACHE0_EN

The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
BYPASS_L1_ICACHE1_EN

The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
BYPASS_L1_ICACHE2_EN

Reserved
BYPASS_L1_ICACHE3_EN

Reserved
BYPASS_L1_DCACHE_EN

The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd